The world’s compute demands are exploding as artificial intelligence, edge devices, and data-hungry applications push the limitations of chip topography harder than ever. At the same time, data centrers, which we have come to rely on as the backbone of our digital lives, are consuming staggering amounts of energy. It is conceivable that they will eventually use as much electricity as entire countries.

The promised productivity boost that AI is slated to unleash is heavily constrained by access to power. With energy infrastructure taking years to come online, a growing emissions profile, and reliance on an energy supply chain that is not entirely within our control, it becomes mission-critical to find ways to limit server energy consumption. So early last year, we set out on a deep dive expedition to study the most effective ways to reduce a data center’s energy consumption and found that at the earliest phase of the value chain, the processor level, improving a chip’s efficiency has a powerful waterfall effect, significantly reducing requirements and demand from grid infrastructure.

Saving 10% of power at the processor level translates to roughly 30% energy savings across the data center. The premise that Neologic set to challenge was that the way we design chips today cannot scale to meet the future we are building.  

When we first met Avi Messica and Ziv Leshem, we were struck, not just by their technical vision, but also by their mission. They weren’t pitching an incremental improvement to chips; they were daring to rethink the very rules of semiconductor design. What they set out to achieve sounded impossible to most people in the industry we spoke with, but this is exactly what ignited our curiosity to learn more.

Moore’s Law, which powered 50 years of semiconductor progress, has plateaued. Transistors keep shrinking, but the gains are harder to extract. Traditional CMOS-based architectures are hitting their physical and economic limits. Power leakage, massive transistor redundancy, and skyrocketing design costs are slowing innovation just as AI workloads demand more than ever. It was obvious that we were at a true inflection point - either we accept the rule of diminishing returns or break the confines that defined the industry for decades and find a new way forward.

Neologic’s quasi-CMOS architecture blends the strengths of traditional CMOS with novel circuit topologies to deliver something that was thought to be unattainable: up to 30% lower power consumption, fewer transistors, and higher performance. What’s key is that it is compatible with today’s processors and foundries without requiring any exotic materials or processes—just a redesign of the logic itself.

Why is this important?

Because it’s practical.

Neologic isn’t asking the semiconductor industry to reinvent its infrastructure. The technology works within existing fabrication flows, which means lower cost, easier and faster adoption, and real-world viability.

Avi and Ziv showed their strong conviction that compute power shouldn’t be constrained by physics or energy. They see a future where chips run cooler, faster, and more efficiently, unlocking the potential of AI and edge computing without draining the planet’s resources.

Their vision isn’t just about disrupting semiconductors but about enabling the next era of intelligent systems.

Our “Why We Invested?” centre around the duality of technological audaciousness and commercial viability that Neologic embodies. The young startup is tackling one of the hardest problems in hardware at exactly the moment the world needs it most. Why else? Because we firmly believe that we have crossed that chasm where it is no longer optional to scale AI sustainably and grow data centers without consuming unsustainable amounts of energy. It is essential if we want to allow the semiconductor industry to continue driving human progress.

‍

- by Talia Rafaeli, Partner

---